CVE-2025-45006: n/a
Source CVE Database V5
Not known to be exploited · CVSS 9.1 Critical.
Data as of 25 Oct 2026, 19:02 UTC
- EPSS
- 0.4% chance of exploitation in 30 days – higher than 40% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:HExploitation evidence
Disclosed: evidence found.
CVE published 1 Jul 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 2026-10-25.
What to do
AI-suggested
To mitigate CVE-2025-45006, organizations should: 1) Identify all devices and systems using the affected open-source RISC-V processor implementation, focusing on embedded and IoT devices. 2) Monitor for patches or updates from the maintainers of the RISC-V processor codebase and apply them promptly once available. 3) Implement strict physical security controls to prevent unauthorized access to devices running vulnerable processors, reducing the risk of physical memory attacks. 4) Employ defense-in-depth strategies such as hardware-based memory protection units (MPUs) or trusted execution environments (TEEs) to limit the impact of privileged memory access violations. 5) Conduct thorough security assessments and penetration testing on RISC-V-based devices to identify potential privilege escalation paths that could lead to exploitation of this vulnerability. 6) Restrict and monitor privileged code execution capabilities on affected devices, ensuring that only trusted and verified code runs with elevated privileges. 7) Collaborate with hardware and software vendors to stay informed about vulnerability disclosures and remediation timelines. These steps go beyond generic advice by focusing on the unique aspects of this vulnerability related to physical memory access and privileged mode exploitation in RISC-V processors.
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.