CVE-2025-51677: n/a
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior.
AI Analysis
Technical Summary
This vulnerability concerns a discrepancy between the Register Transfer Level (RTL) design and the netlist implementation of the OR1200 CPU output port in the openRISC project. The mismatch can lead to unexpected CPU behavior, potentially impacting the reliability or correctness of the CPU's operation. The issue was identified in a specific commit (83ac6b), but no further technical details or exploit methods are described. No remediation or patch information is available at this time.
Potential Impact
The impact is an unexpected behavior of the OR1200 CPU output port due to the mismatch between RTL and netlist. The exact consequences are not detailed, and there is no evidence of exploitation in the wild. The vulnerability could affect system stability or correctness where this CPU design is used.
Mitigation Recommendations
Patch status is not yet confirmed — check the vendor advisory for current remediation guidance. No official fix or mitigation steps have been provided. Users of the openRISC OR1200 CPU design should monitor vendor communications for updates.
CVE-2025-51677: n/a
Description
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior.
AI-Powered Analysis
Machine-generated threat intelligence
Technical Analysis
This vulnerability concerns a discrepancy between the Register Transfer Level (RTL) design and the netlist implementation of the OR1200 CPU output port in the openRISC project. The mismatch can lead to unexpected CPU behavior, potentially impacting the reliability or correctness of the CPU's operation. The issue was identified in a specific commit (83ac6b), but no further technical details or exploit methods are described. No remediation or patch information is available at this time.
Potential Impact
The impact is an unexpected behavior of the OR1200 CPU output port due to the mismatch between RTL and netlist. The exact consequences are not detailed, and there is no evidence of exploitation in the wild. The vulnerability could affect system stability or correctness where this CPU design is used.
Mitigation Recommendations
Patch status is not yet confirmed — check the vendor advisory for current remediation guidance. No official fix or mitigation steps have been provided. Users of the openRISC OR1200 CPU design should monitor vendor communications for updates.
Technical Details
- Data Version
- 5.2
- Assigner Short Name
- mitre
- Date Reserved
- 2025-06-16T00:00:00.000Z
- Cvss Version
- null
- State
- PUBLISHED
- Remediation Level
- null
Threat ID: 6a5b5eac2d1edb114c7fb237
Added to database: 07/18/2026, 11:08:28 UTC
Last enriched: 07/18/2026, 11:51:40 UTC
Last updated: 07/18/2026, 13:12:59 UTC
Views: 4
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