CVE-2026-45944: Linux kernel · Race Condition
Affects Linux kernelSource CVE Database V5
Not known to be exploited · CVSS 7.5 High · fixed in d2138abc8f0a7fce4101b7229b43b06811ed083d : patch Linux kernel soon.
Data as of 26 Oct 2026, 14:18 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 2% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
- CISA SSVC
- Exploitation
- No evidence of active exploitation and no public proof of concept
- Automatable
- Attackers cannot reliably automate steps 1–4 of the kill chain
- Technical impact
- Total control over the software or total information disclosure
CISA SSVC assessment, 2026-10-16.
- Patch
- Available – fixed in d2138abc8f0a7fce4101b7229b43b06811ed083d, c716a59e9977d751e5eb54bcfa6a80124cb5067b, c1e4f1dccbe9d7656d1c6872ebeadb5992d0aaa2 +2
CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:H/I:H/A:HExploitation evidence
Disclosed: evidence found.
CVE published 27 May 2026
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 26 Oct 2026.
What to do
Upgrade to a fixed release listed under Affected software.
Affected software
| Product | Affected | Fixed in |
|---|---|---|
| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in– |
Description
In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down context entry When tearing down a context entry, the current implementation zeros the entire 128-bit entry using multiple 64-bit writes. This creates a window where the hardware can fetch a "torn" entry — where some fields are already zeroed while the 'Present' bit is still set — leading to unpredictable behavior or spurious faults. While x86 provides strong write ordering, the compiler may reorder writes to the two 64-bit halves of the context entry. Even without compiler reordering, the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. Align with the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the context entry first to signal the transition of ownership from hardware to software. 2. Use dma_wmb() to ensure the cleared bit is visible to the IOMMU. 3. Perform the required cache and context-cache invalidation to ensure hardware no longer has cached references to the entry. 4. Fully zero out the entry only after the invalidation is complete. Also, add a dma_wmb() to context_set_present() to ensure the entry is fully initialized before the 'Present' bit becomes visible.
References
- git.kernel.org/stable/c/ab4aeab2d630e68be60ccbea3fcf76fa7c281a18 (opens in a new tab)
- git.kernel.org/stable/c/c716a59e9977d751e5eb54bcfa6a80124cb5067b (opens in a new tab)
- git.kernel.org/stable/c/d2138abc8f0a7fce4101b7229b43b06811ed083d (opens in a new tab)
- git.kernel.org/stable/c/a922dbafb4a674d958d702038232d09a30daf770 (opens in a new tab)
- git.kernel.org/stable/c/c1e4f1dccbe9d7656d1c6872ebeadb5992d0aaa2 (opens in a new tab)