CVE-2026-53354: Linux kernel · Race Condition
Affects Linux kernelSource CVE Database V5
Mentioned vulnerabilities
Not known to be exploited · CVSS 8.8 High · fixed in e717a4d08779f1a28d6e0275e75040b12c33c753 : patch Linux kernel soon.
Data as of 26 Oct 2026, 14:05 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 0% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
- CISA SSVC
- Exploitation
- No evidence of active exploitation and no public proof of concept
- Automatable
- Attackers cannot reliably automate steps 1–4 of the kill chain
- Technical impact
- Total control over the software or total information disclosure
CISA SSVC assessment, 2026-10-16.
- Patch
- Available – fixed in e717a4d08779f1a28d6e0275e75040b12c33c753, d4fd4282204044fdedd1e42abbe70a9206f74ec0, cfd391e74134db664feb499d43af286380b10ba8 +6
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:HExploitation evidence
Disclosed: evidence found.
CVE published 1 Jul 2026
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 26 Oct 2026.
What to do
Upgrade to a fixed release listed under Affected software.
Affected software
| Product | Affected | Fixed in |
|---|---|---|
| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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| LinuxLinux | Affected
| Fixed in
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Description
In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.
References
- git.kernel.org/stable/c/925058203229403008d77a52b1e63e2ae5f4a3cf (opens in a new tab)
- git.kernel.org/stable/c/8364384ae82fbffdf8968abaac3455ed854da18d (opens in a new tab)
- git.kernel.org/stable/c/7c3ad9365079e716b57d2363d3081ee7680cc18e (opens in a new tab)
- git.kernel.org/stable/c/e717a4d08779f1a28d6e0275e75040b12c33c753 (opens in a new tab)
- git.kernel.org/stable/c/4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8 (opens in a new tab)
- git.kernel.org/stable/c/d4fd4282204044fdedd1e42abbe70a9206f74ec0 (opens in a new tab)
- git.kernel.org/stable/c/1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd (opens in a new tab)
- git.kernel.org/stable/c/1268c64e2bcb6e968152990e87bd10c440fcc9c0 (opens in a new tab)
- git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8 (opens in a new tab)