Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect branch predictors for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access
Source GCVE Database
Not known to be exploited · CVSS 5.7 Medium.
Data as of 29 Oct 2026, 22:52 UTC
Thin evidence
One scorer or none| CNA (intel) | CVSS 4.0 | 5.7 |
|---|---|---|
| CNA (intel) | CVSS 3.1 | 5.6 |
CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:NExploitation evidence
Disclosed: evidence found.
CVE published 13 May 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponized: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 29 Oct 2026.
Description
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect branch predictors for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
References
- nvd.nist.gov/vuln/detail/CVE-2024-45332 (opens in a new tab)
- comsec.ethz.ch/research/microarch/branch-privilege-injection (opens in a new tab)
- intel.com/content/www/us/en/security-center/advisory/intel-sa-01247.html (opens in a new tab)
- lists.debian.org/debian-lts-announce/2025/05/msg00021.html (opens in a new tab)
- openwall.com/lists/oss-security/2025/05/13/7 (opens in a new tab)