CVE-2024-28956VulnerabilityPublished 1 Jul 2025Updated 5 Nov 2026

Red Hat Security Advisory: microcode_ctl security update

Affects Red Hat microcode_ctlSource GCVE Database

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Not known to be exploited.

Data as of 5 Nov 2026, 16:37 UTC

Severity

Medium

Rated by Threat Radar · No CVSS score from NVD or the CNA

Exploitation evidence

Disclosed: evidence found.
CVE published 1 Jul 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponized: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors

A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 5 Nov 2026.

Disclosed: The CVE record is public on cve.org. Its publication is t = 0.
Detectable: A public nuclei template can find exposed instances, for defenders and attackers alike.
Weaponized: A Metasploit exploit module or Exploit-DB entry exists (Metasploit scanner modules do not count), or CISA SSVC or the CVSS exploit maturity reports a public proof of concept.
Exploited in the wild: CISA KEV lists it, CISA SSVC rates exploitation active, or a source reports attacks.
Observed by OffSeq Mirage: OffSeq Mirage honeypot sensors recorded attack traffic for this CVE, or found exposed hosts without attack traffic.

Moments are spaced evenly, not to scale; a dashed line marks a gap of six months or more. Deltas count from t = 0. Sources that give only a date (CISA KEV, Exploit-DB, or a time of exactly 00:00Z) read “same day” rather than hours. Metasploit modules carry the flaw’s disclosure date, not their release date, and nuclei templates carry no date, so both appear above but not on the timeline.

What to do

AI-suggested

Red Hat has released an official security update for microcode_ctl on Red Hat Enterprise Linux 8.2 AUS. Users should apply the update as described in the Red Hat advisory (RHSA-2025:10126) and the referenced article https://access.redhat.com/articles/11258 to remediate the vulnerabilities. Since this is an official fix, applying the update fully mitigates the issue.

Description

The microcode_ctl package for Red Hat Enterprise Linux provides microcode updates for Intel and AMD processors. A security update addressing CVE-2024-28956 has been released with a moderate severity rating. The update is available for Red Hat Enterprise Linux 8.2 Advanced Update Support. The advisory references multiple CVEs but focuses on CVE-2024-28956. No specific CVSS score is provided in the advisory, and no known exploits in the wild have been reported.

Reports on CVE-2024-28956

GCP-2025-024GCP Compute Engine Security2026-10-26

Impact

The vulnerabilities addressed by this update affect the microcode_ctl package responsible for processor microcode updates. The impact is rated moderate by Red Hat, indicating potential security issues that could affect system integrity or stability if unpatched. There are no known exploits in the wild, and no detailed CVSS score is provided to quantify the risk further.

Summary

Red Hat issued a security advisory (RHSA-2025:10126) for the microcode_ctl package, which delivers microcode updates for Intel and AMD processors on Red Hat Enterprise Linux 8.2 AUS. The advisory addresses CVE-2024-28956 among other CVEs, rating the impact as moderate. The update mitigates vulnerabilities related to processor microcode that could potentially affect system stability or security. The advisory includes links to updated package versions and instructions for applying the update. No public exploit code or active exploitation has been reported.

CWE-1421Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution (opens in a new tab)
Base weakness
A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.
Architecture and Design
Hardware designers may choose to engineer the processor's pipeline to prevent architecturally restricted data from being used by operations that can execute transiently.
Architecture and Design
Hardware designers may choose not to share microarchitectural resources that can contain sensitive data, such as fill buffers and store buffers.
Architecture and Design
Hardware designers may choose to sanitize specific microarchitectural state (for example, store buffers) when the processor transitions to a different context, such as whenever a system call is invoked.
From MITRE CWE, MITRE CAPEC and OWASP (Top 10, OpenCRE).
CWE-1423Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution (opens in a new tab)
Base weakness
Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.
Architecture and Design
The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.
Architecture and Design
Hardware designers may choose to use microarchitectural bits to tag predictor entries. For example, each predictor entry may be tagged with a kernel-mode bit which, when set, indicates that the predictor entry was created in kernel mode.
Architecture and Design
Hardware designers may choose to sanitize microarchitectural predictor state (for example, branch prediction history) when the processor transitions to a different context, for example, whenever a system call is invoked.
From MITRE CWE, MITRE CAPEC and OWASP (Top 10, OpenCRE).
CWE-696Incorrect Behavior Order (opens in a new tab)
Class weakness
The product performs multiple related behaviors, but the behaviors are performed in the wrong order in ways that may produce resultant weaknesses.
Attack patterns
Padding Oracle Crypto Attack (opens in a new tab)
From MITRE CWE, MITRE CAPEC and OWASP (Top 10, OpenCRE).
CWE-1419Incorrect Initialization of Resource (opens in a new tab)
Class weakness
The product attempts to initialize a resource but does not correctly do so, which might leave the resource in an unexpected, incorrect, or insecure state when it is accessed.
Implementation
Choose the safest-possible initialization for security-related resources.
Implementation
Ensure that each resource (whether variable, memory buffer, register, etc.) is fully initialized.
Implementation
Pay close attention to complex conditionals or reset sources that affect initialization, since some paths might not perform the initialization.
From MITRE CWE, MITRE CAPEC and OWASP (Top 10, OpenCRE).

References

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Exploitation evidence

What to do

Description

Reports on CVE-2024-28956

AI analysisMachine-generated, updated 5 Nov 2026, 16:37 UTC

WeaknessesCWE-1421, CWE-1423, CWE-696 +1

Technical details

References

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