CVE-2024-42279: Linux kernel · spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
Affects Linux kernelSource GCVE Database
Not known to be exploited · CVSS 7.8 High.
Data as of 30 Oct 2026, 13:34 UTC
Thin evidence
One scorer or none| CNA (Linux) | CVSS 3.1 | 7.8 |
|---|
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:HExploitation evidence
Disclosed: evidence found.
CVE published 17 Aug 2024
Detectable: no evidence on record.
No public nuclei template indexed
Weaponized: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 30 Oct 2026.
Description
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
References
- git.kernel.org/stable/c/950375a0ba7d6c82ea5b5a44dd48a9e41fa45826 (opens in a new tab)
- git.kernel.org/stable/c/3feda3677e8bbe833c3a62a4091377a08f015b80 (opens in a new tab)
- git.kernel.org/stable/c/45e03d35229b680b79dfea1103a1f2f07d0b5d75 (opens in a new tab)
- git.kernel.org/stable/c/9cf71eb0faef4bff01df4264841b8465382d7927 (opens in a new tab)