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VulnerabilityPublished Updated

CVE-2026-50719: Use of Function with Inconsistent Implementations

Source CVE Database V5

0

Not known to be exploited · CVSS 6.8 Medium.

Data as of 26 Oct 2026, 13:47 UTC

CVSS 3.1 base score
6.8Medium
How severe the flaw is on the 0–10 CVSS scale.
EPSS
0.1% chance of exploitation in 30 days – higher than 3% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H

Exploitation evidence

  1. Disclosed: evidence found.

    CVE published 19 Aug 2026

  2. Detectable: no evidence on record.

    No public nuclei template indexed

  3. Weaponised: no evidence on record.

    No public exploit code indexed in Metasploit or Exploit-DB

  4. Exploited in the wild: no evidence on record.

    Not in CISA KEV and no source reports exploitation

  5. Observed by OffSeq Mirage: no evidence on record.

    No attack traffic recorded by OffSeq Mirage sensors

A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 26 Oct 2026.

What to do

AI-suggested

Since the vulnerability requires physical write access to boot media, mitigation may involve physical security controls to prevent unauthorized access. Monitor vendor advisories for any future firmware or hardware mitigations.

Description

The Ingenic T41 SoC boot ROM, and likely the T32, T40, and A1 variants, contain a vulnerability in their boot process. The boot ROM parses and executes an attacker-controlled init table from the SPL header before verifying secure boot state or signature. This init table parser allows 32-bit writes to SRAM, enabling an attacker with physical write access to boot media to disable secure boot checks. This leads to acceptance of unsigned or modified first-stage boot code, bypassing secure boot protections. The issue has been hardware-validated on the T41 and confirmed by ROM analysis on related SoCs.

References

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