CVE-2025-54515: AMD Versal™ Adaptive SoC Devices · Improper Validation of Specified Quantity in Input
Affects AMD Versal™ Adaptive SoC DevicesSource CVE Database V5
Not known to be exploited · CVSS 1.0 Low.
Data as of 26 Oct 2026, 14:05 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 2% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:NExploitation evidence
Disclosed: evidence found.
CVE published 23 Nov 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 26 Oct 2026.
What to do
AI-suggested
- Monitor AMD and trusted firmware vendors for official patches or firmware updates addressing CVE-2025-54515 and apply them promptly once available.
- Restrict local access to devices running AMD Versal Adaptive SoCs to trusted personnel only, minimizing the risk of exploitation requiring local privileges.
- Implement strict user authentication and authorization controls on systems hosting these SoCs to prevent unauthorized user interaction.
- Employ hardware security modules or trusted execution environments to isolate critical firmware components and reduce the attack surface.
- Conduct regular security audits and firmware integrity checks to detect unauthorized modifications or anomalous PSCI command behavior.
- For embedded and industrial deployments, ensure network segmentation and monitoring to detect suspicious local activity that could precede exploitation attempts.
- Educate system administrators and security teams about the specific nature of this vulnerability to enhance incident response readiness.
- Consider deploying runtime protection mechanisms that can detect and block anomalous power state commands or firmware calls.
Description
The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.