In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs… (CVE-2026-53354)
A vulnerability affecting certain Arm CPUs in the Linux kernel has been addressed. The issue involves errata where a broadcast TLBI;DSB sequence may complete before the global observation of writes translated by an invalidated TLB entry. This does not affect the invalidation of TLB entries themselves but impacts memory access completion. The mitigation involves applying an additional TLBI;DSB sequence to ensure proper global observation of memory writes. The ARM64_WORKAROUND_REPEAT_TLBI workaround is recommended for affected CPUs. This vulnerability is tracked as CVE-2026-53354 and affects Linux kernel version 3.0.
AI Analysis
Technical Summary
The vulnerability concerns an erratum in various Arm CPUs where a broadcast TLBI;DSB sequence can complete prematurely, before all memory writes translated by an invalidated TLB entry are globally observed. This affects the completion of memory accesses but not the invalidation of TLB entries. The recommended mitigation is to follow any affected TLBI;DSB sequence with an additional TLBI;DSB operation to ensure all memory write effects are globally observed. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate this issue. This vulnerability is identified as CVE-2026-53354 and has been resolved in Linux kernel version 3.0.
Potential Impact
The vulnerability impacts memory access completion on affected Arm CPUs, potentially causing memory writes translated by invalidated TLB entries to not be globally observed in a timely manner. This can lead to consistency issues in memory operations. The invalidation of TLB entries themselves is not affected. The CVSS vector indicates high impact on confidentiality, integrity, and availability, but no known exploits are reported in the wild.
Mitigation Recommendations
Apply the ARM64_WORKAROUND_REPEAT_TLBI workaround for affected CPUs as recommended by Arm. This involves following any affected TLBI;DSB sequence with an additional TLBI;DSB operation to ensure proper global observation of memory writes. Update silicon errata documentation accordingly. Linux kernel version 3.0 includes the resolution for this vulnerability. Patch status beyond this version is not explicitly stated; check vendor advisories for updates.
In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs… (CVE-2026-53354)
Description
A vulnerability affecting certain Arm CPUs in the Linux kernel has been addressed. The issue involves errata where a broadcast TLBI;DSB sequence may complete before the global observation of writes translated by an invalidated TLB entry. This does not affect the invalidation of TLB entries themselves but impacts memory access completion. The mitigation involves applying an additional TLBI;DSB sequence to ensure proper global observation of memory writes. The ARM64_WORKAROUND_REPEAT_TLBI workaround is recommended for affected CPUs. This vulnerability is tracked as CVE-2026-53354 and affects Linux kernel version 3.0.
CVSS v3.1
Score 8.8high
Affected software
AI-Powered Analysis
Machine-generated threat intelligence
Technical Analysis
The vulnerability concerns an erratum in various Arm CPUs where a broadcast TLBI;DSB sequence can complete prematurely, before all memory writes translated by an invalidated TLB entry are globally observed. This affects the completion of memory accesses but not the invalidation of TLB entries. The recommended mitigation is to follow any affected TLBI;DSB sequence with an additional TLBI;DSB operation to ensure all memory write effects are globally observed. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate this issue. This vulnerability is identified as CVE-2026-53354 and has been resolved in Linux kernel version 3.0.
Potential Impact
The vulnerability impacts memory access completion on affected Arm CPUs, potentially causing memory writes translated by invalidated TLB entries to not be globally observed in a timely manner. This can lead to consistency issues in memory operations. The invalidation of TLB entries themselves is not affected. The CVSS vector indicates high impact on confidentiality, integrity, and availability, but no known exploits are reported in the wild.
Mitigation Recommendations
Apply the ARM64_WORKAROUND_REPEAT_TLBI workaround for affected CPUs as recommended by Arm. This involves following any affected TLBI;DSB sequence with an additional TLBI;DSB operation to ensure proper global observation of memory writes. Update silicon errata documentation accordingly. Linux kernel version 3.0 includes the resolution for this vulnerability. Patch status beyond this version is not explicitly stated; check vendor advisories for updates.
Technical Details
- Gcve Source
- db.gcve.eu
- Csaf Category
- csaf_vex
- Csaf Version
- 2.0
- Publisher
- Microsoft Security Response Center
- Advisory Id
- msrc_CVE-2026-53354
- Cve Count
- 1
- Additional Cves
- []
- Cvss Version
- 3.1
Threat ID: 6a4f6c1a68715ace43155769
Added to database: 07/09/2026, 09:38:34 UTC
Last enriched: 07/19/2026, 01:22:45 UTC
Last updated: 07/31/2026, 19:24:50 UTC
Views: 62
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