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CVE-2024-26670: Vulnerability in Linux Linux

Medium
VulnerabilityCVE-2024-26670cvecve-2024-26670
Published: Tue Apr 02 2024 (04/02/2024, 06:43:31 UTC)
Source: CVE
Vendor/Project: Linux
Product: Linux

Description

In the Linux kernel, the following vulnerability has been resolved: arm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD Currently the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround isn't quite right, as it is supposed to be applied after the last explicit memory access, but is immediately followed by an LDR. The ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround is used to handle Cortex-A520 erratum 2966298 and Cortex-A510 erratum 3117295, which are described in: * https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en * https://developer.arm.com/documentation/SDEN1873361/1600/?lang=en In both cases the workaround is described as: | If pagetable isolation is disabled, the context switch logic in the | kernel can be updated to execute the following sequence on affected | cores before exiting to EL0, and after all explicit memory accesses: | | 1. A non-shareable TLBI to any context and/or address, including | unused contexts or addresses, such as a `TLBI VALE1 Xzr`. | | 2. A DSB NSH to guarantee completion of the TLBI. The important part being that the TLBI+DSB must be placed "after all explicit memory accesses". Unfortunately, as-implemented, the TLBI+DSB is immediately followed by an LDR, as we have: | alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternative_else_nop_endif | alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 | ldr lr, [sp, #S_LR] | add sp, sp, #PT_REGS_SIZE // restore sp | eret | alternative_else_nop_endif | | [ ... KPTI exception return path ... ] This patch fixes this by reworking the logic to place the TLBI+DSB immediately before the ERET, after all explicit memory accesses. The ERET is currently in a separate alternative block, and alternatives cannot be nested. To account for this, the alternative block for ARM64_UNMAP_KERNEL_AT_EL0 is replaced with a single alternative branch to skip the KPTI logic, with the new shape of the logic being: | alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 | [ ... KPTI exception return path ... ] | .L_skip_tramp_exit_\@: | | ldr lr, [sp, #S_LR] | add sp, sp, #PT_REGS_SIZE // restore sp | | alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | tlbi vale1, xzr | dsb nsh | alternative_else_nop_endif | eret The new structure means that the workaround is only applied when KPTI is not in use; this is fine as noted in the documented implications of the erratum: | Pagetable isolation between EL0 and higher level ELs prevents the | issue from occurring. ... and as per the workaround description quoted above, the workaround is only necessary "If pagetable isolation is disabled".

AI-Powered Analysis

AILast updated: 06/28/2025, 02:25:29 UTC

Technical Analysis

CVE-2024-26670 addresses a vulnerability in the Linux kernel specifically related to the ARM64 architecture's handling of speculative unprivileged loads. The issue stems from an incorrect implementation of the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround designed to mitigate errata in Cortex-A520 and Cortex-A510 processors (erratum 2966298 and 3117295 respectively). These errata relate to speculative execution vulnerabilities where unprivileged speculative loads could potentially leak sensitive information or cause unexpected behavior. The workaround involves executing a sequence of instructions after all explicit memory accesses but before returning to user space (EL0). This sequence includes a non-shareable Translation Lookaside Buffer Invalidate (TLBI) instruction followed by a Data Synchronization Barrier (DSB) to ensure completion of the TLBI. However, the original implementation placed the TLBI and DSB instructions immediately before a load instruction (LDR), violating the requirement that these instructions must come after all explicit memory accesses. This incorrect placement could allow the erratum to be exploited, potentially undermining kernel security boundaries. The patch reworks the kernel's exception return path to place the TLBI and DSB instructions immediately before the exception return (ERET) instruction, ensuring they occur after all explicit memory accesses. This fix is only applied when Kernel Page Table Isolation (KPTI) is disabled, which is acceptable because KPTI itself prevents the erratum from being exploitable by isolating page tables between user and kernel space. The vulnerability affects Linux kernel versions identified by specific commit hashes, indicating it is a recent issue in the ARM64 kernel codebase. No known exploits are currently reported in the wild. This vulnerability is subtle and specific to ARM64 processors affected by the errata, and it requires the system to have pagetable isolation disabled, which is uncommon in modern secure configurations. However, systems running affected ARM64 processors without KPTI enabled remain at risk.

Potential Impact

For European organizations, the impact of CVE-2024-26670 primarily concerns systems running Linux on ARM64 hardware, particularly those using Cortex-A520 or Cortex-A510 processors. These processors are increasingly common in energy-efficient servers, embedded devices, and edge computing platforms. If pagetable isolation is disabled, an attacker with local unprivileged access could exploit this vulnerability to bypass kernel memory protections, potentially leading to privilege escalation or information disclosure. This could compromise the confidentiality and integrity of sensitive data and critical system operations. The impact is more pronounced in environments where ARM64 Linux servers handle sensitive workloads without KPTI enabled, such as certain cloud providers, telecom infrastructure, or IoT gateways. Given the growing adoption of ARM64 in European data centers and industrial control systems, the vulnerability poses a risk to sectors like telecommunications, manufacturing, and public infrastructure. However, the requirement for pagetable isolation to be disabled and the absence of known exploits reduce the immediate threat level. Organizations using standard hardened Linux distributions with KPTI enabled are less likely to be affected. Nonetheless, failure to patch could expose systems to advanced local attackers aiming to escalate privileges or extract kernel memory contents.

Mitigation Recommendations

European organizations should take the following specific mitigation steps: 1) Verify if their Linux systems run on ARM64 processors, especially Cortex-A520 or Cortex-A510 cores, and check kernel versions against the affected commits. 2) Ensure that Kernel Page Table Isolation (KPTI) is enabled, as this effectively mitigates the vulnerability by isolating kernel and user space page tables. 3) Apply the latest Linux kernel patches that include the fix for CVE-2024-26670, ensuring the workaround is correctly implemented. 4) For embedded or specialized devices where kernel updates are challenging, consider disabling untrusted local user access or employing additional sandboxing to limit exploitation potential. 5) Monitor vendor advisories for firmware or microcode updates addressing the underlying ARM errata. 6) Conduct security audits to confirm that no configurations disable pagetable isolation inadvertently. 7) Employ runtime security tools capable of detecting anomalous kernel behavior or privilege escalation attempts. These targeted actions go beyond generic patching by emphasizing configuration validation and hardware-specific considerations.

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Technical Details

Data Version
5.1
Assigner Short Name
Linux
Date Reserved
2024-02-19T14:20:24.150Z
Cisa Enriched
true
Cvss Version
null
State
PUBLISHED

Threat ID: 682d9821c4522896dcbdda1d

Added to database: 5/21/2025, 9:08:49 AM

Last enriched: 6/28/2025, 2:25:29 AM

Last updated: 8/5/2025, 1:22:29 PM

Views: 13

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