CVE-2025-0003: AMD Xilinx Run Time (XRT) · Improper Resource Locking
Affects AMD Xilinx Run Time (XRT)Source CVE Database V5
Not known to be exploited · CVSS 7.3 High.
Data as of 26 Oct 2026, 06:26 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 8% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:3.1/AV:L/AC:L/PR:L/UI:R/S:C/C:H/I:L/A:LExploitation evidence
Disclosed: evidence found.
CVE published 24 Nov 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 2026-10-26.
What to do
AI-suggested
1. Monitor AMD and Xilinx official channels for patches addressing CVE-2025-0003 and apply them promptly once released. 2. Restrict local access to systems running XRT to trusted users only, employing strict access controls and least privilege principles. 3. Implement endpoint detection and response (EDR) solutions to monitor for unusual activity related to XRT processes or memory corruption indicators. 4. Conduct regular audits of user accounts and running processes on systems with XRT installed to detect unauthorized usage. 5. Use application whitelisting to prevent execution of unauthorized code that could exploit the vulnerability. 6. Educate users about the risks of interacting with untrusted applications or files that could trigger the vulnerability. 7. In environments where patching is delayed, consider isolating FPGA-accelerated systems from general user access or network segments to reduce attack surface. 8. Employ runtime protections such as memory corruption mitigations (e.g., ASLR, DEP) if supported by the platform. 9. Review and harden system configurations related to XRT and FPGA management interfaces to minimize exposure. 10. Prepare incident response plans specific to FPGA-related vulnerabilities and ensure readiness to respond to potential exploitation attempts.
Description
Inadequate lock protection within Xilinx Run time may allow a local attacker to trigger a Use-After-Free condition potentially resulting in loss of confidentiality or availability