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CVE-2025-0029VulnerabilityPublished

CVE-2025-0029: AMD EPYC™ 9005 Series Processors · Detection of Error Condition Without Action

Affects AMD EPYC™ 9005 Series ProcessorsSource CVE Database V5

0

Not known to be exploited · CVSS 1.8 Low.

Data as of 25 Oct 2026, 19:02 UTC

CVSS 4.0 base score
1.8Low
How severe the flaw is on the 0–10 CVSS scale.
EPSS
0.1% chance of exploitation in 30 days – higher than 2% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:4.0/AV:L/AC:H/AT:N/PR:H/UI:N/VC:N/VI:L/VA:N/SC:N/SI:L/SA:N

Exploitation evidence

  1. Disclosed: evidence found.

    CVE published 10 Feb 2026

  2. Detectable: no evidence on record.

    No public nuclei template indexed

  3. Weaponised: no evidence on record.

    No public exploit code indexed in Metasploit or Exploit-DB

  4. Exploited in the wild: no evidence on record.

    Not in CISA KEV and no source reports exploitation

  5. Observed by OffSeq Mirage: no evidence on record.

    No attack traffic recorded by OffSeq Mirage sensors

A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 2026-10-25.

What to do

Affected software

ProductAffectedFixed in
AMDAMD EPYC™ 9005 Series ProcessorsAffected–Fixed in–
AMDAMD EPYC™ Embedded 9005 Series ProcessorsAffected–Fixed in–

AI-suggested

1. Enforce strict access controls and privilege separation on host systems to prevent unauthorized local high-privileged access. 2. Monitor and audit host activities related to DMA operations and SEV-SNP guest interactions to detect anomalies indicative of selective DMA write drops. 3. Maintain up-to-date firmware and microcode from AMD, applying patches promptly once released to address this vulnerability. 4. Employ hardware-based attestation and integrity verification mechanisms for SEV-SNP guests to detect memory integrity violations. 5. Limit the exposure of critical workloads to hosts with unpatched AMD EPYC 9005 processors or consider temporary migration to unaffected hardware. 6. Collaborate with AMD and cloud service providers to receive timely vulnerability disclosures and remediation guidance. 7. Implement layered security controls including host-based intrusion detection and endpoint protection to reduce the risk of privilege escalation enabling exploitation.

Description

Improper handling of error condition during host-induced faults can allow a local high-privileged attack to selectively drop guest DMA writes, potentially resulting in a loss of SEV-SNP guest memory integrity

References

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