CVE-2025-20067: Intel(R) CSME and Intel(R) SPS · Information Disclosure
Affects Intel(R) CSME and Intel(R) SPSSource CVE Database V5
Not known to be exploited · CVSS 6.8 Medium.
Data as of 26 Oct 2026, 06:26 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 5% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:4.0/AV:L/AC:L/AT:P/PR:H/UI:N/VC:H/VI:N/VA:N/SC:H/SI:N/SA:NExploitation evidence
Disclosed: evidence found.
CVE published 12 Aug 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 2026-10-26.
What to do
AI-suggested
To mitigate this vulnerability, European organizations should: 1) Monitor and restrict privileged access rigorously, employing strong access controls and auditing to detect unauthorized privilege escalations. 2) Apply Intel's firmware updates and patches as soon as they become available, as firmware-level vulnerabilities require vendor-supplied fixes. 3) Employ endpoint detection and response (EDR) solutions to monitor for suspicious local activity indicative of exploitation attempts. 4) Use hardware-based security features such as Intel Trusted Execution Technology (TXT) and secure boot to reduce the risk of firmware tampering. 5) Conduct regular security assessments and penetration testing focusing on privilege escalation and side-channel attack vectors. 6) Segment critical systems and limit local administrative access to reduce the attack surface. 7) Educate system administrators about the risks of timing side-channel attacks and the importance of maintaining strict privilege hygiene.
Description
Observable timing discrepancy in firmware for some Intel(R) CSME and Intel(R) SPS may allow a privileged user to potentially enable information disclosure via local access.