CVE-2025-63384: rocket-chip · Incorrect Privilege Assignment
Affects rocket-chipSource CVE Database V5
Not known to be exploited · CVSS 6.5 Medium.
Data as of 26 Oct 2026, 09:15 UTC
- EPSS
- 0.3% chance of exploitation in 30 days – higher than 25% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:NExploitation evidence
Disclosed: evidence found.
CVE published 10 Nov 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 26 Oct 2026.
What to do
Affected software
| Product | Affected | Fixed in |
|---|---|---|
GitHubchipsalliance/rocket-chippkg:github/chipsalliance/rocket-chipOther threats | Affected
| Fixed in– |
Check your own hosts for these packages with threat-finder (opens in a new tab), our free open-source scanner.
AI-suggested
1. Monitor vendor communications closely for official patches or microcode updates addressing CVE-2025-63384 and apply them promptly once available. 2. Implement strict privilege separation policies and limit supervisor-level code execution to trusted, verified components to reduce the risk of exploitation. 3. Employ runtime monitoring and anomaly detection to identify unusual privilege escalations or unexpected machine-mode operations. 4. For embedded and IoT devices, enforce secure boot and firmware integrity checks to prevent unauthorized code execution at supervisor level. 5. Conduct thorough security audits of systems using RISC-V Rocket-Chip processors to identify potential exposure and isolate vulnerable devices where feasible. 6. Engage with hardware vendors and system integrators to understand the deployment scope and receive guidance on secure configurations. 7. Consider network segmentation and access controls to limit exposure of vulnerable devices to untrusted networks. 8. Develop incident response plans that include scenarios involving privilege escalation on embedded platforms.
Description
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.