CVE-2025-9612: PCI Express Integrity and Data Encryption (PCIe IDE) Specification · Improper Resource Shutdown or Release
Affects PCI Express Integrity and Data Encryption (PCIe IDE) SpecificationSource CVE Database V5
Not known to be exploited · CVSS 5.1 Medium.
Data as of 26 Oct 2026, 07:57 UTC
- EPSS
- 0.1% chance of exploitation in 30 days – higher than 3% of CVEsExploit Prediction Scoring System: the likelihood attackers will use this flaw soon.
CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:U/C:L/I:L/A:NExploitation evidence
Disclosed: evidence found.
CVE published 9 Dec 2025
Detectable: no evidence on record.
No public nuclei template indexed
Weaponised: no evidence on record.
No public exploit code indexed in Metasploit or Exploit-DB
Exploited in the wildExploited: no evidence on record.
Not in CISA KEV and no source reports exploitation
Observed by OffSeq MirageSeen by Mirage: no evidence on record.
No attack traffic recorded by OffSeq Mirage sensors
A missing step is not evidence of safety. Sources: cve.org (opens in a new tab), the Metasploit, Exploit-DB and nuclei-templates index as of 2026-10-26.
What to do
Affected software
| Product | Affected | Fixed in |
|---|---|---|
| PCI-SIG PCI Express Integrity and Data Encryption (PCIe IDE) Specification | Affected
| Fixed in– |
AI-suggested
Mitigation of CVE-2025-9612 requires a multi-layered approach beyond generic advice. First, organizations should conduct a thorough hardware and firmware audit to verify that PCIe devices implementing IDE encryption enforce strict TLP ordering and tag uniqueness as per best practices, even if the specification lacks explicit guidance. Vendors should be engaged to provide firmware updates or design revisions addressing this flaw. Second, implement enhanced monitoring and anomaly detection on PCIe bus traffic to identify unusual packet reordering or replay attempts, using hardware performance counters or specialized PCIe bus analyzers. Third, enforce strict physical security controls to limit local or physical access to systems with vulnerable PCIe devices, including secure server rooms and tamper-evident seals. Fourth, segment critical systems to minimize the risk of lateral movement by attackers with physical access. Finally, maintain up-to-date inventories of PCIe hardware and track vendor advisories for patches or specification updates. Organizations should also consider deploying endpoint detection and response (EDR) solutions capable of detecting suspicious hardware-level anomalies. Collaboration with PCI-SIG and hardware vendors to accelerate specification clarifications and patch development is essential.
Description
An issue was discovered in the PCI Express (PCIe) Integrity and Data Encryption (IDE) specification, where insufficient guidance on Transaction Layer Packet (TLP) ordering and tag uniqueness may allow encrypted packets to be replayed or reordered without detection. This can enable local or physical attackers on the PCIe bus to violate data integrity protections.